1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device including bipolar transistors and a method of manufacturing the same.
2. Description of the Background Art
In recent years, performance of industrial equipments such as computers has been remarkably improved. A Bi-CMOS (Bipolar Complementary Metal Oxide Semiconductor) structure in which a bipolar transistor and a CMOS transistor are formed on the same semiconductor substrate has attracted the attention from the aspect of complying with the aforementioned remarkable performance. The Bi-CMOS structure can achieve high-speed operation from of the bipolar transistor, and high integration and low power consumption feature of the CMOS transistor.
A conventional semiconductor is below particularly in connection with the structure of Bi-CMOS structure including bipolar transistors.
FIG. 62 is a cross section schematically showing a structure of the conventional semiconductor device. Referring to FIG. 62, the Bi-CMOS structure has a bipolar transistor region 510, an nMOS transistor region 520 and a pMOS transistor region 540.
In bipolar transistor region 510, an n.sup.+ buried layer 503 is formed on a surface of a p.sup.- semiconductor substrate 501. An n.sup.- epitaxial growth layer 505 and an n.sup.+ diffusion layer 513 for leading out a collector are formed on the surface of n buried layer 503.
A p base region 507 and a p.sup.+ external base region 511 adjoining to each other are formed on the surface of n.sup.- epitaxial growth layer 505. An n emitter region 509 is formed on p.sup.- base region 507.
A first interlayer insulating film 563 is formed over the surface of bipolar transistor 510. First interlayer insulating film 563 is provided with a contact hole 563a reaching n.sup.+ emitter region 509. An emitter electrode 515 is formed on the surface of first interlayer insulating film 563 and is in contact with n.sup.+ emitter region 509 through contact hole 563a. Emitter electrode 515 is made of polycrystalline silicon doped with arsenic (As).
Emitter electrode 515 is covered with a second interlayer insulating film 565 formed on the surface of first interlayer insulating film 563. Second interlayer insulating film 565 is provided with a contact hole 565a reaching emitter electrode 515. A conductive layer 571a is in contact with emitter electrode 515 through contact hole 565a.
First and second interlayer insulating films 563 and 565 are provided with contact holes 565b and 565c, which reach p.sup.+ external base region 511 and n.sup.+ diffusion layer 513, respectively. Conductive layers 571b and 571c are in contact with p.sup.+ external base region 511 and n.sup.+ diffusion region 513 through contact holes 565b and 565c, respectively.
In nMOS transistor region 520, a p.sup.- well region 523 is formed on the surface of p.sup.- semiconductor substrate 501. A plurality of nMOS transistors 530 are formed on the surface of p.sup.- well region 523.
Each nMOS transistor 530 includes a pair of n-type source/drain regions 525, a gate oxide film 527 and a gate electrode 529.
Each pair of n-type source/drain regions 525 are formed on p.sup.- well region 523 with a predetermined space between each other. n-type source/drain region 525 has an LDD (Lightly Doped Drain) structure formed of a relatively lightly doped n.sup.- impurity region 525a and a relatively heavily doped n.sup.+ impurity region 525b. A gate electrode 529 is formed on a region between paired n-type source/drain regions 525 with a gate oxide film 527 therebetween.
The nMOS transistor 530 is covered with first interlayer insulating film 563. First interlayer insulating film 563 is provided with an aperture 563b which reaches one of paired source/drain regions 525. An interconnection layer 535 is formed on first interlayer insulating film 563 and is in contact with n-type source/drain region 525 through aperture 563b. Interconnection layer 535 is made of polycrystalline silicon doped with arsenic.
The surface of interconnection layer 535 is covered with second interlayer insulating film 565, which is provided with a contact hole 565d reaching interconnection layer 535. A conductive layer 571d is in contact with interconnection layer 535 through contact hole 565d.
First and second interlayer insulating films 563 and 565 are provided with a contact hole 565e reaching n-type source/drain region 525. A conductive layer 571e is in contact with n-type source/drain region 525 through contact hole 565e.
In pMOS transistor region 540, an n.sup.+ buried layer 541 is formed on the surface of p.sup.- semiconductor substrate 501. An n.sup.- well region 543 is formed on the surface of n.sup.+ buried layer 541. A pMOS transistor 550 is formed on the surface of n.sup.- well region 543.
The pMOS transistor 550 has a pair of p.sup.+ source/drain regions 545, a gate oxide film 547 and a gate electrode 549.
A pair of p.sup.+ source/drain regions 545 are formed on the surface of n.sup.- well region 543 with a predetermined space between each other. Gate electrode 549 is formed on a region between paired p.sup.+ source/drain regions 545 with a gate oxide film 547 therebetween.
pMOS transistor 550 is covered with first and second interlayer insulating films 563 and 565. First and second interlayer insulating films 563 and 565 are provided with contact holes 565f reaching paired p.sup.+ source/drain regions 545. Conductive layers 571f are in contact with p.sup.- source/drain regions 545 through contact holes 565f.
Element isolating oxide films 561 are provided for electrically isolating regions 510, 520 and 540 and others from each other.
A method of manufacturing the conventional semiconductor device is described below.
FIGS. 63 to 83 are schematic cross sections showing a process of manufacturing the conventional semiconductor device in accordance with the order of process steps. Referring first to FIG. 63, a silicon oxide film 581 is formed on the whole surface of p.sup.- semiconductor substrate 501, for example, by thermal oxidation. Thereafter, silicon oxide film 581 is patterned into a predetermined configuration. Using silicon oxide film 581 thus patterned as a mask, impurity such as antimony (Sb) is implanted into p.sup.- semiconductor substrate 501. Then, heat treatment at about 1100.degree. C. is executed for about 2 hours, whereby n.sup.+ layers 503a and 541a are formed on the surface of p.sup.- semiconductor substrate 501. Thereafter, silicon oxide film 581 is removed.
Referring to FIG. 64, n.sup.- epitaxial growth layer 505 is formed on the whole surface of p.sup.- semiconductor substrate 501. Thereby, such a structure is completed that n.sup.+ buried layers 503 and 541 are buried between p.sup.- semiconductor substrate 501 and an n.sup.- epitaxial growth layer 505.
Referring to FIG. 65, an n-type impurity such as phosphorus (P) is introduced into n.sup.- epitaxial growth layer 543 located above n.sup.+ buried layer 541 and then is diffused. Thereby, n.sup.- well region 543 is formed above n.sup.+ buried layer 541. p-type impurity such as boron (B) is introduced into a predetermined region in n.sup.- epitaxial growth layer 505 and then is diffused. Thereby, p.sup.- well region 523 is formed.
Referring to FIG. 66, element isolating oxide films 561 are formed at predetermined regions, for example, by an LOCOS (Local Oxidation of Silicon) method.
Referring to FIG. 67, a silicon oxide film (SiO.sub.2) 583 and a silicon nitride film (Si.sub.3 N.sub.4) 585, which have apertures at predetermined regions and are 300 .ANG. and 1000 .ANG. in thickness, respectively, are formed by deposition successively on the whole surface. Using silicon oxide film 583 and silicon nitride film 585 as a mask, the structure is exposed to an atmosphere containing, e.g., POCl.sub.3. Thereby, phosphorus is diffused into n.sup.- epitaxial growth layer 505 to form n.sup.+ diffusion layer 513 for leading the collector. Thereafter, silicon nitride film 585 and silicon oxide film 583 are successively removed.
Referring to FIG. 68, a thermal oxidation film 527a is formed on the whole surface by thermal oxidation. Then, an LPCVD (Low Pressure Chemical Vapor Deposition) method is used to form a polycrystalline silicon film 529a and a silicon oxide film 531a each having a thickness of about 2000 .ANG. by successive deposition. The silicon oxide film 531a and polycrystalline silicon film 529a are patterned into a predetermined configuration by photolithography and etching.
Referring to FIG. 69, gate electrodes 529 and 549 having the predetermined configuration are formed by the aforementioned patterning.
Referring to FIG. 70, photoresist 591a is applied to the whole surface, and then is exposed and developed. Thereby, a resist pattern 591a exposing the nMOS transistor region is formed. Using resist pattern 591a and gate electrode 529 as a mask, n-type impurity is implanted to form relatively lightly doped n.sup.- impurity region 525a on the surface of p.sup.- well region 523. Thereafter, resist pattern 591a is removed.
Referring to FIG. 71, a silicon oxide film 533a is formed over the whole surface. Thereafter, anisotropic etching is effected on silicon oxide film 533a.
Referring to FIG. 72, by the aforementioned anisotropic etching, side wall oxide films 533 and 553 covering side walls of gate electrodes 529 and 549 are formed. This anisotropic etching removes thin silicon oxide film 527a at a lower level, whereby gate oxide films 527 and 547 are formed.
Referring to FIG. 73, photoresist 591b is applied to the whole surface, and is exposed and developed. Thereby, resist pattern 591b exposing the nMOS transistor region is formed. Using resist pattern 591b, gate electrodes 529 and side wall oxide films 533 as a mask, n-type impurity is implanted. This implantation forms relatively heavily doped n.sup.+ impurity regions 525b on the surface of p.sup.- well region. The n.sup.- impurity regions 525a and n.sup.+ impurity regions 525b form n-type source/drain regions 525 having a LDD structure. Thereby, nMOS transistors 530 are formed. Thereafter, resist pattern 591 is removed.
Referring to FIG. 74, photoresist 591c is applied to the whole surface, and is exposed and developed to form resist pattern 591c which exposes the pMOS transistor region and a predetermined region of the bipolar transistor. Using resist pattern 591c as a mask, p-type impurity is implanted into n.sup.- well region 543 and n.sup.- epitaxial growth layer 505. This implantation forms p.sup.+ source/drain regions 545 at the pMOS transistor region and also forms p.sup.+ external base region 511 at the bipolar transistor region. Thereby, pMOS transistor 550 is formed. Thereafter, resist pattern 591c is removed.
Referring to FIG. 75, photoresist 591d is applied to the whole surface, and is exposed and developed to form resist pattern 591d which exposes a predetermined region of the bipolar transistor. Using resist pattern 591d as a mask, p-type impurity is implanted into n.sup.- epitaxial growth layer 505. By this implantation and others, p.sup.- base region 507 adjoining to p.sup.+ external base region 511 are formed. Thereafter, resist pattern 591d is removed.
Referring to FIG. 76, first interlayer insulating film 563 made of, e.g., a silicon oxide film is formed on the whole surface. The surface of first interlayer insulating film 563 has an unevenness reflecting a difference in level of lower layers.
Referring to FIG. 77, photoresist 591e is applied to the whole surface, and is exposed and developed to form resist pattern 591e having a predetermined configuration. Using this resist pattern 591e as a mask, processing such as RIE (Reactive Ion Etching) is effected on the first interlayer insulating film 563. In first interlayer insulating film 563, the aforementioned processing such as RIE forms emitter aperture 563a which partially exposes the surface of p.sup.+ base region 507, and also forms aperture 563b which exposes n-type source/drain region 525. Thereafter, resist pattern 591e is removed.
Referring to FIG. 78, the LPCVD method is executed to form polycrystalline silicon film 515a on the whole surface of first interlayer insulating film 563.
Referring to FIG. 79, arsenic is implanted into the whole surface of polycrystalline silicon film 515a. Thereafter, RTA (Rapid Thermal Annealing) or the like is executed to effect high temperature thermal treatment thereon, for example, at a temperature of about 1050.degree. C. for about 30 seconds. Thereby, arsenic is uniformly diffused into doped polycrystalline silicon film 515b, and is also diffused into n.sup.- epitaxial growth layer 505, so that n.sup.+ emitter region 509 is formed.
Referring to FIG. 80, doped polycrystalline silicon film 515b is patterned into a predetermined configuration by photolithography and etching. This forms emitter electrode 515 connected to n.sup.+ emitter region 509 through emitter aperture 563a, and interconnection layer 535 connected to n-type source/drain region 525 through aperture 563b.
Referring to FIG. 81, second interlayer insulating film 565 is formed on the whole surface of first interlayer insulating film 563 to cover emitter electrode 515 and interconnection layer 535. Photoresist 591f is applied to the whole surface of second interlayer insulating film 565, and is exposed and developed. Resist pattern 591f thus formed and having a predetermined configuration is used as a mask for effecting anisotropic etching. This etching forms contact holes 565a, 565b, 565c, 565d, 565e and 565f. Thereafter, resist pattern 591f is removed.
Referring to FIG. 82, conductive layers 571a, 571b, 571c, 571d, 571e and 571f are formed, which are in contact with conductive regions or others exposed at the bottoms through contact holes 565a, 565b, 565c, 565d, 565e and 591f, respectively.
In the conventional method of manufacturing the semiconductor device described above, it is necessary to carry out heat treatment by RTA in the process shown in FIG. 79. According to the RTA, wafer only is thermally processed at a high temperature by lamp heating. The heat treatment by the RTA is required because of the following reason.
In the conventional method of manufacturing the semiconductor device, emitter electrode 515 and interconnection layer 535 shown in FIG. 62 are formed by patterning the polycrystalline silicon film into which impurity is ion-implanted.
More specifically, at the process shown in FIGS. 78 and 79, impurity is ion-implanted into polycrystalline silicon film 515a. The impurity is injected from above the substrate and perpendicularly into the substrate. Therefore, non-implanted regions in which an impurity has not been implanted are formed along the side walls of aperture 563b and emitter aperture 563a in doped polycrystalline silicon film 515b within regions S.sub.1 and S.sub.2 in FIG. 79.
FIG. 83 is an enlarged fragmentary cross section showing region S.sub.1 in FIG. 79 for explaining the fact that there is generated the non-implanted regions. Referring to FIG. 83, the side wall of aperture 563b has a height H.sub.2 from the surface of p.sup.- well region 523. This height H.sub.2 is much larger than a thickness T.sub.p of doped polycrystalline silicon film 515a. Therefore, it is very difficult to ion-implant the impurity into portions along the side walls.
In particular, in the MOS transistor region, a gate part portion must be formed on the substrate. Therefore, height H.sub.2 of side wall of first interlayer insulating film 563 is large due to a height H.sub.1 of the gate portion (i.e., gate oxide film 527, gate electrode 529 and insulating film 531). Meanwhile, in the bipolar transistor region, a gate electrode is not necessary. Therefore, height H.sub.2 of side wall of aperture 563b formed in the MOS transistor region is larger than the height of side wall of emitter aperture formed in the bipolar transistor region within region S.sub.2 in FIG. 79. As is apparent from the above, impurity is hardly implanted into the portion of polycrystalline silicon film 515a along the high side wall of aperture 563b.
When the sidewall has the non-implanted region, a so-called non-diffusion region 515a, i.e., region into which impurity is not diffused, is formed at the sidewall of doped polycrystalline silicon film 563b as shown in FIG. 84, unless high temperature heat treatment such as RTA is not effected.
Interconnection layer 515b generally has the interconnection resistance as shown in FIG. 85. The interconnection resistance is represented as combination of resistances of portions other than that within aperture 563b (which will be referred to as "resistances of flat portions"), resistances of the side wall of aperture 563b and a resistance of a contact portion (boundary surface) between aperture 563b and source/drain region 525. Therefore, if non-diffusion region 515a is formed, the resistance of the sidewall increases, so that the interconnection resistance of interconnection layer 515b locally increases.
In order to prevent increase of the interconnection resistance, it is necessary to uniformly diffuse the impurity for preventing generation of the non-diffusion region. Therefore, the high temperature heat treatment by RTA is required so as to uniformly diffuse the impurity up to the sidewall of aperture 563b as shown in FIG. 84.
The conventional method of manufacturing the semiconductor device requires the heat treatment by RTA as described above.
Due to the heat treatment by RTA, the conventional semiconductor device and the method of manufacturing the same have the following problems: (1) the degree of integration cannot be improved; and (2) the interconnection resistance of the emitter electrode and others can be reduced. These problems are described below in greater detail.
(1) The degree of integration.
Elimination of the heat treatment is essential in order to improve the degree of integration and the performance of the conventional semiconductor device according to a scaling rule. The same is especially true with respect to the MOS transistor.
Referring to FIG. 86, the heat treatment by RTA is executed for uniform diffusion of impurity into doped polycrystalline silicon film 515b as described above. The high temperature heat treatment, however, causes n.sup.+ impurity region 525b to spread in a depth direction indicated by arrows J.sub.1 and a width direction indicated by arrows J.sub.2. Thus, a so-called shallow junction cannot be formed.
In such case, n.sup.+ source/drain regions 525b spread as shown by dotted line in the figure, so that punch-through is likely to occur. Since n.sup.- impurity regions 525a are taken into n.sup.+ impurity regions 525b, it is difficult to reduce a hot electron effect.
In order to achieve the high integration, a gate length L.sub.G1 of gate electrode 529 may be reduced, in which case a distance between adjoining n.sup.+ source/drain regions 525b decreases. Therefore, heat treatment by RTA will promote the disadvantageous punch-though and impair a characteristic relating to resistance against hot electrons. Therefore, gate length L.sub.G1 of gate electrode 529 cannot be reduced, which makes it difficult to improve the degree of integration. As described above, the conventional method of manufacturing the semiconductor device cannot sufficiently improve the degree of integration because it requires the high temperature heat treatment such as RTA.
(2) The interconnection resistance of the emitter electrode and others.
Generally, if arsenic and phosphorus are introduced into polycrystalline silicon, segregation of arsenic at grain boundaries in the polycrystalline silicon is more likely than phosphorus. Therefore, if arsenic and phosphorus are individually introduced at the same concentration into the polycrystalline silicon, a concentration of carriers (activated impurity in grains) of arsenic would be lower than that of phosphorus by a degree corresponding to the segregation of arsenic at the grain boundaries.
FIG. 87 shows a relationship between an annealing temperature and a carrier concentration in the case where phosphorus and arsenic are individually introduced into polycrystalline silicon at a concentration of 2.times.10.sup.19 cm.sup.-3. As is seen from FIG. 87, in the case where arsenic and phosphorus are individually implanted to attain the same concentration, the concentration of carriers of phosphorus is higher than that of arsenic regardless of the annealing temperature. If these are introduced to have the same concentration, therefore, phosphorus can achieve a lower resistance. From a viewpoint of the low resistance, therefore, polycrystalline silicon doped with phosphorus is more suitable to the interconnection layer than that doped with arsenic.
FIG. 88 shows a relationship between an impurity concentration and a resistivity when phosphorus and arsenic are individually introduced into polycrystalline silicon. In the case of arsenic shown in FIG. 88, the resistivity is saturated and will no longer lower when the concentration attains 2.times.10.sup.20 cm.sup.-3 or more. Meanwhile, in the case of phosphorus, the resistivity lowers even at the concentration higher than the aforementioned value. As can be seen also from this result, polycrystalline silicon doped with phosphorus is more suitable to the interconnection layer than polycrystalline silicon doped with arsenic from the viewpoint of low resistance.
However, phosphorus is diffused more rapidly than arsenic. Therefore, if polycrystalline silicon 515b were doped with phosphorus at the conventional manufacturing step shown in FIG. 79, and then RTA were effected to form emitter region 509 in FIG. 80, emitter region 509 would spread excessively, in which case an intended base width might not be obtained.
FIG. 89 shows a reason by which the intended base width cannot be obtained if the polycrystalline silicon is doped with phosphorus. Referring to FIG. 89, high temperature heat treatment promotes diffusion of phosphorus from emitter electrode 515 toward p.sup.- base region 507 in a direction indicated by arrow J. Thereby, n.sup.+ emitter region 509 is formed deep, resulting in reduction of a width W.sub.2 of p.sup.- base region 507 immediately under n.sup.+ emitter region 509. If width W.sub.2 of p.sup.- base region 507 is small, a collector-emitter breakdown voltage of the npn bipolar transistor decreases.
In view of the reduction of the breakdown voltage, it has been difficult to introduce phosphorus at a high concentration into emitter electrode 515. In the conventional semiconductor device, therefore, the phosphorus concentration cannot be larger than 1.times.10.sup.20 cm.sup.-3 if phosphorus is introduced into emitter electrode 515. Although it is preferable to introduce phosphorus from the viewpoint of the interconnection resistance, the concentration of phosphorus cannot be high because of the aforementioned reason, so that it is impossible to reduce the interconnection resistance of emitter electrode 515 in the prior art.
Consequently, according to the conventional semiconductor device and the method of manufacturing the same, it is impossible to further reduce the overall interconnection resistance of the emitter electrode while maintaining a good breakdown voltage characteristic.